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| Ultima descărcare din IBN: 2022-10-25 10:25 |
 SM ISO690:2012GRIŢCOV, Sergiu, SOROCHIN, Gherman, ŞESTACOVA, Tatiana. Pseudo-ring testing of the FPGA memory using software Nios processor. In: Telecommunications, Electronics and Informatics, Ed. 6, 24-27 mai 2018, Chișinău. Chișinău, Republica Moldova: 2018, Ed. 6, pp. 328-331. ISBN 978-9975-45-540-4. |
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| Telecommunications, Electronics and Informatics Ed. 6, 2018 |
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Conferința "Telecommunications, Electronics and Informatics" 6, Chișinău, Moldova, 24-27 mai 2018 | ||||||
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In this paper we review FPGA of the Altera company and we present an example of a ‘software’ microcontroller based on Nios processor creating. Also an algorithm for memory self-testing was developed and implemented on C language. This algorithm provides self-testing of the Nios and FPGA memory. Also this algorithm is based on pseudo-ring testing methods, which allow to significantly reduce hardware resources for self-realization. |
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| Cuvinte-cheie Field Programmable Gate Array (FPGA), Nios, self-testing, psedo-ring method |
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Google Scholar Export
<meta name="citation_title" content="Pseudo-ring testing of the FPGA memory using software Nios processor"> <meta name="citation_author" content="Griţcov Sergiu"> <meta name="citation_author" content="Sorochin Gherman"> <meta name="citation_author" content="Şestacova Tatiana"> <meta name="citation_publication_date" content="2018"> <meta name="citation_collection_title" content="Telecommunications, Electronics and Informatics"> <meta name="citation_volume" content="Ed. 6"> <meta name="citation_firstpage" content="328"> <meta name="citation_lastpage" content="331"> <meta name="citation_pdf_url" content="https://ibn.idsi.md/sites/default/files/imag_file/328-331_1.pdf">
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