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SM ISO690:2012 GRIŢCOV, Sergiu, SOROCHIN, Gherman, ŞESTACOVA, Tatiana. Pseudo-ring testing of the FPGA memory using software Nios processor. In: Telecommunications, Electronics and Informatics, Ed. 6, 24-27 mai 2018, Chișinău. Chișinău, Republica Moldova: 2018, Ed. 6, pp. 328-331. ISBN 978-9975-45-540-4. |
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Telecommunications, Electronics and Informatics Ed. 6, 2018 |
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Conferința "Telecommunications, Electronics and Informatics" 6, Chișinău, Moldova, 24-27 mai 2018 | ||||||
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Pag. 328-331 | ||||||
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In this paper we review FPGA of the Altera company and we present an example of a ‘software’ microcontroller based on Nios processor creating. Also an algorithm for memory self-testing was developed and implemented on C language. This algorithm provides self-testing of the Nios and FPGA memory. Also this algorithm is based on pseudo-ring testing methods, which allow to significantly reduce hardware resources for self-realization. |
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Cuvinte-cheie Field Programmable Gate Array (FPGA), Nios, self-testing, psedo-ring method |
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DataCite XML Export
<?xml version='1.0' encoding='utf-8'?> <resource xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance' xmlns='http://datacite.org/schema/kernel-3' xsi:schemaLocation='http://datacite.org/schema/kernel-3 http://schema.datacite.org/meta/kernel-3/metadata.xsd'> <creators> <creator> <creatorName>Griţcov, S.</creatorName> <affiliation>Universitatea Tehnică a Moldovei, Moldova, Republica</affiliation> </creator> <creator> <creatorName>Sorochin, G.</creatorName> <affiliation>Universitatea Tehnică a Moldovei, Moldova, Republica</affiliation> </creator> <creator> <creatorName>Şestacova, T.</creatorName> <affiliation>Universitatea Tehnică a Moldovei, Moldova, Republica</affiliation> </creator> </creators> <titles> <title xml:lang='en'>Pseudo-ring testing of the FPGA memory using software Nios processor</title> </titles> <publisher>Instrumentul Bibliometric National</publisher> <publicationYear>2018</publicationYear> <relatedIdentifier relatedIdentifierType='ISBN' relationType='IsPartOf'>978-9975-45-540-4</relatedIdentifier> <subjects> <subject>Field Programmable Gate Array (FPGA)</subject> <subject>Nios</subject> <subject>self-testing</subject> <subject>psedo-ring method</subject> </subjects> <dates> <date dateType='Issued'>2018</date> </dates> <resourceType resourceTypeGeneral='Text'>Conference Paper</resourceType> <descriptions> <description xml:lang='en' descriptionType='Abstract'><p>In this paper we review FPGA of the Altera company and we present an example of a ‘software’ microcontroller based on Nios processor creating. Also an algorithm for memory self-testing was developed and implemented on C language. This algorithm provides self-testing of the Nios and FPGA memory. Also this algorithm is based on pseudo-ring testing methods, which allow to significantly reduce hardware resources for self-realization.</p></description> </descriptions> <formats> <format>application/pdf</format> </formats> </resource>