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| Ultima descărcare din IBN: 2022-10-25 10:25 |
 SM ISO690:2012GRIŢCOV, Sergiu, SOROCHIN, Gherman, ŞESTACOVA, Tatiana. Pseudo-ring testing of the FPGA memory using software Nios processor. In: Telecommunications, Electronics and Informatics, Ed. 6, 24-27 mai 2018, Chișinău. Chișinău, Republica Moldova: 2018, Ed. 6, pp. 328-331. ISBN 978-9975-45-540-4. |
| EXPORT metadate: Google Scholar Crossref CERIF DataCite Dublin Core |
| Telecommunications, Electronics and Informatics Ed. 6, 2018 |
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Conferința "Telecommunications, Electronics and Informatics" 6, Chișinău, Moldova, 24-27 mai 2018 | ||||||
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In this paper we review FPGA of the Altera company and we present an example of a ‘software’ microcontroller based on Nios processor creating. Also an algorithm for memory self-testing was developed and implemented on C language. This algorithm provides self-testing of the Nios and FPGA memory. Also this algorithm is based on pseudo-ring testing methods, which allow to significantly reduce hardware resources for self-realization. |
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| Cuvinte-cheie Field Programmable Gate Array (FPGA), Nios, self-testing, psedo-ring method |
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Dublin Core Export
<?xml version='1.0' encoding='utf-8'?> <oai_dc:dc xmlns:dc='http://purl.org/dc/elements/1.1/' xmlns:oai_dc='http://www.openarchives.org/OAI/2.0/oai_dc/' xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance' xsi:schemaLocation='http://www.openarchives.org/OAI/2.0/oai_dc/ http://www.openarchives.org/OAI/2.0/oai_dc.xsd'> <dc:creator>Griţcov, S.</dc:creator> <dc:creator>Sorochin, G.</dc:creator> <dc:creator>Şestacova, T.</dc:creator> <dc:date>2018</dc:date> <dc:description xml:lang='en'><p>In this paper we review FPGA of the Altera company and we present an example of a ‘software’ microcontroller based on Nios processor creating. Also an algorithm for memory self-testing was developed and implemented on C language. This algorithm provides self-testing of the Nios and FPGA memory. Also this algorithm is based on pseudo-ring testing methods, which allow to significantly reduce hardware resources for self-realization.</p></dc:description> <dc:source>Telecommunications, Electronics and Informatics (Ed. 6) 328-331</dc:source> <dc:subject>Field Programmable Gate Array (FPGA)</dc:subject> <dc:subject>Nios</dc:subject> <dc:subject>self-testing</dc:subject> <dc:subject>psedo-ring method</dc:subject> <dc:title>Pseudo-ring testing of the FPGA memory using software Nios processor</dc:title> <dc:type>info:eu-repo/semantics/article</dc:type> </oai_dc:dc>
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