The key problem of the digital circuit (DC) testability always was the elaboration of the efficient test generation methods, their importance grew once with the transition to the new generation of integrated circuits. The structural complexity and the enhanced functionality of a DC lead to enamors expenses due to test generation. A lot more obvious became the necessity for elaboration the demands, principles and methods for the design for testability (DFT) – DFT of the DC’s. The theoretic bases for the DC’s testability continued to evolve in the same time with the elaboration of the methodology and concepts of DFT. In 1966, Roth elaborates DALG-I [1]. Schneider [2] brings a counterexample DC, in which the error 6≡0 couldn’t be detected according to the DALG-I, also the test existed. In 1967 the DALG-II [3] algorithm appears which guarantees the generation of the test for detecting the error 6≡0. In [4] it is demonstrated that the 6≡0 error is a specific one. In [5, 6] it is demonstrated the possibility of apparition for an unsolvable logic conflicts, and in [7] – the redundancy of this DC. The present paper confirms the redundancy of the Schneider’s DC.