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 SM ISO690:2012SUDACEVSCHI, Viorica, ABABII, Victor, CALUGARI, Dmitri, BORDIAN, Dimitrie. Time delay evaluation in printed circuit boards based on timed hard petri nets. In: Sielmen: Proceedings of the 11th international conference on electromechanical and power systems, Ed. 11, 11-13 octombrie 2017, Iași. New Jersey, SUA: Institute of Electrical and Electronics Engineers Inc., 2017, Ediția 11, pp. 59-61. ISBN 978-153861846-2. DOI: https://doi.org/10.1109/SIELMEN.2017.8123292 |
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 Sielmen Ediția 11, 2017 |
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Conferința "Sielmen" 11, Iași, Romania, 11-13 octombrie 2017 | ||||||
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| DOI:https://doi.org/10.1109/SIELMEN.2017.8123292 | ||||||
| Pag. 59-61 | ||||||
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This paper presents a synthesis method for delay time evaluation in the printed circuit boards based on Timed Hard Petri Nets. For the specification and modeling of the delay time evaluation system, Timed Synchronous Petri Nets (TSPN) are used. The transition to the hardware description of the system is achieved by translating the TSPN into Timed Hard Petri Net (THPN). The implementation of the delay time evaluation system is done by direct mapping of the THPN into the reconfigurable hardware architecture (FPGA). |
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| Cuvinte-cheie Delay time, FPGA, HDL, Printed circuit boards, Timed Hard Petri nets |
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