The aim of study is to investigate a possibility to electrochemically form microbumps of Co-W alloy, because it recently has gained attraction as a novel barrier against copper diffusion. In order to be applied in flip-chip technology the barrier layers should be void-free and uniformly deposited on the entire area of a die to ensure high reliability and high performance of wafer bump-solder interface. To meet these requirements, a number of electrodepositions in potentiostatic and galvanostatic modes were carried out from a citrate electrolyte, at various pH of solutions and temperatures on patterned wafers. Morphology and composition of the depositions were characterized. It was found out that Co-W void-free mirobumps can be electrodeposited at pH 5 and room temperature only. Electrodeposition at higher pH or temperature causes damage of the photoresist and not uniform filling of recesses. The electrodeposition under stirring can essentially improve the overall uniformity and flatness of the deposited array, which is very important for future applications of Co-W layers for interconnects. High quality arrays of Co-W alloys electrodeposits where achieved under both potentiostatic and galvanostatic conditions. The resistivity of obtained Co-W barrier layer dependently on the thickness of electrodeposits was 24·10^-8 W m for 0.5 mm and 45 10^-8 W m for 2 mm, and these values are close to other materials used as a barrier.   Successful route for the Cu/Co-W/Sn tri-layered bump electrodeposition without internal cracks, delamination or any other unwanted artefacts was achieved. In this case Co-W alloy acts as a barrier layer preventing diffusion of Sn from the top to the bottom Cu layer during soldering. The intermediate Co-W alloy consisted of 4-5 at. % of W is a solid solution of components [1]. Therefore, we assumed the same solubility of Sn in Co-W alloy and Co in Sn as in the pure Co. After Sn has been molten at 250 ^oC, on the boundary Sn/Co the solubility of Co in molten Sn is as low as 0.04 wt.% at and according to Sn-Co phase diagram there are CoSn, CoSn2, and CoSn3 intermetallic phases in the Sn rich part of binary Sn-Co system [2]. In deeper layers at this temperature the equilibrium between solid phases of a-Co₃Sn₂, b-Co₃Sn₂ should exist. If formed barrier layer is thick enough, the diffusion of Sn into Cu layer will be neglected during soldering. The diffusion of Sn into Cu layer was evaluated experimentally by XPS depth profiling. After annealing at 250 °C for 3 and 30 min stronger overlapping of Sn and Co was observed therefore, it is assumed that during annealing significant diffusion of Sn into Co-W takes place. In the overlapped region concentration ratio between Sn and Co is close to unity and this indicates the formation of stechoemetric CoSn alloy. Nevertheless, it is important to notice that despite the significant Sn diffusion into Co-W layer, Sn does not diffuse into Cu. Later observation confirms that Co-W can be used as an effective diffusion barrier in analysed tri-layered Sn/Co-W/Cu structures.