In order to study the ITO/n-Si solar cell interface variation, depending on the silicon surface treatment processes, the electrical properties of these structures were investigated. Solar cells based on the above mentioned junctions were obtained using the relatively low-temperature spray-pyrolysis technique, compared to the temperature of solar cells on the base of p-n junction‘s fabrication [1]. The state of the interfaces of the investigated structures was modified by using the Si wafers etching processes, in the first case. The etching process was absent in the second case and an intermediate native oxide layer on the working surface of the Si plate, before the deposition of the frontal component (ITO) was formed. The results of the voltage-capacitance dependencies investigation have demonstrated the existence of an intermediate layer of ~ 8nm thickness at the Si/ITO interface, when the Si wafers were preventively etched in the mixture of HF and HNO3 acids. The results of the investigation of the cross-section of this structures using transmission electron microscopy (TEM) and the study the X-ray diffraction (XRD), proved the presence of a strongly damaged layer of the same crystalline structure as Si substrate. In the case of silicon wafer structures subjected only to thermal treatment, the thickness of the intermediate layer, determined by the voltage-capacitance dependence is ~ 4nm. Electron energy loss spectroscopy (EELS) analysis confirmed the presence of SiOx layer, and the images, obtained by TEM microscopy, demonstrate that the SiOx layer thickness is in the order of 1-2nm.