Nowadays, two types of templates are widely used for nanofabrication purposes, namely porous Al2O3 and etched ion track membranes based either on inorganic materials or on organic polymers. Both, porous Al2O3 and etched ion track membranes, however, exhibit high resistivity and therefore they often play a passive role in nanofabrication processes. In this connection an important technological task is the development of cost-effective semiconductor nanotemplates which properties could be easily controlled by external illumination, applied electric fields etc. We report on controlled fabrication of semiconductor nanotemplates using anodic etching of III-V (GaP, InP) and II-VI (ZnSe, ZnCdS, CdSe) crystalline substrates, self-organized processes being evidenced and studied in some materials. The walls of the porous semiconductor skeleton, exhibiting good electrical conductivity in comparison with the walls of dielectric nanotemplates, create good conditions for uniform nucleation of metal dots. Recently, the so-called “hopping electrodeposition” mechanism was proposed to explain the electroplating of one monolayer of gold nanodots on porous semiconductor structures. Besides, we succeeded to electrochemically grow arrays of metal nanowires and nanotubes embedded in semiconductor nanotemplates, without any activation of the pore’s wall. In particular, uniform deposition of Pt on the inner surface of pores was demonstrated, regardless of the pore shape (e.g. circular, triangular-prism like pores etc.).