Recent progress in AI is largely attributed to the development of machine learning, especially in the algorithm and neural network models. On the other hand, hardware is on the critical path for the future of AI in the big data era. The rapid development of embedded intelligence for machine learning applications is causing the systems to grow more and more complex. FPGA-based solutions are emerging as the right choice for the implementation of these applications. Obviously, it is very important to understand the impact of architectural parameters on the performance and hardware resources utilization. This paper provides a rigorous analysis of FPGA implementation of Hopfield-like neural networks. The relationship between the hardware resources used to synthesize the data path and those used to provide network connections is discussed, as well as the distribution of these resources and how it depends on the variation in the architectural parameters of the network. The analysis presented in this paper is based on Intel/Altera Cyclone FPGA devices.