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SM ISO690:2012 MAKAREVICH, A., KINASH, A., TOKAR, M.S., CHUBAROV, V.. Performance analysis of PLL components in digital synchronization systems for high-speed applications. In: Systems of Signal Synchronization, Generating and Processing in Telecommunications: SYNCHROINFO 2018, 4-5 iunie 2018, New Jersey. New Jersey, SUA: Institute of Electrical and Electronics Engineers Inc., 2018, p. 0. ISBN 978-153866474-2. DOI: https://doi.org/10.1109/SYNCHROINFO.2018.8457030 |
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Systems of Signal Synchronization, Generating and Processing in Telecommunications 2018 | ||||||
Conferința "Systems of Signal Synchronization, Generating and Processing in Telecommunications" New Jersey, Statele Unite ale Americii, 4-5 iunie 2018 | ||||||
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DOI:https://doi.org/10.1109/SYNCHROINFO.2018.8457030 | ||||||
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The paper presents an analysis of circuit solutions and the results of circuit simulation of one of the options for building a phase-locked frequency (PLL) system containing the following components: phase detector, voltage-controlled oscillator and low-pass filter. All components of the PLL system are implemented within the framework of classical CMOS technology and circuitry. The proposed solutions for CMOS transistors with submicron design standards allow to achieve a significant increase in operating frequencies. |
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Cuvinte-cheie Circuit oscillations, Circuit simulation, CMOS integrated circuits, Locks (fasteners), Low pass filters, Oscillistors, Phase comparators, Signal detection, synchronization, Variable frequency oscillators |
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